Measurement and Prediction of Reliability for Double-Sided Area Array Assemblies

Category: Chip Scale Package (CSP)
Post Date: July 20, 2004
Author(s): Anthony Primavera, Ph.D.,and Mike Meilunas, Universal Instruments Corporation, Binghamton, NY; and James M. Pitarresi, Ph.D., Shiva Kalyan Mandepudi, and Satish Parupalli, Binghamton University, State University of New York, Binghamton, NY

Description
The increasing demand for smaller and faster products in the electronics industry has encouraged the use of CSPs and BGAs assembled on printed circuit boards (PCBs) in a back-to-back double-sided fashion. A critical issue in double-sided assemblies is the thermal cycling reliability performance of the device-to-board level attachment. In this paper, the effects of components placed on both sides of the test board were studied. The components included CSPs, BGAs, QFPs and chip capacitors. To assess the assembly flexural stiffness, a three-point bending measurement was performed and the stiffness used as a parameter for investigating the effect of assembly stiffness on the thermal cycling reliability. Cycles-to-failure were documented for all assemblies and the data were used to calculate the characteristic life. In addition, moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux's crack propagation method.

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