Influence of PCB Parameters on Chip Scale Package Assembly and Reliability - Part I

Category: Chip Scale Package (CSP)
Post Date: July 20, 2004
Author(s): Anthony A. Primavera - Universal Instruments, Surface Mount Technology Laboratory

Description
With the continual miniaturization of electronic components and overall systems, the interconnection between the printed circuit board (PCB) and the component, namely the solder joint becomes smaller as well. This reduction in the physical size of the joint places more demands on the mechanical properties of the solder to ensure joint robustness. In addition to the footprint size reduction, there is an emphasis on total space reduction, often in the form of reduced size in the packaging of the silicon die. As surface mount technology (SMT) migrates towards smaller package dimensions, the physical and thermal characteristics of each material used in the packaging becomes more critical. Very large differences between properties within a package for example layer to layer, as well as between the carrier and the die lead to large internal stresses within a package. Once mounted onto a PCB, the solder joint must typically absorb all strains induced by the expansion of the package and PCB in thermal excursions. For traditional SMT devices, such as quad flat packages, the leads as well as the solder joints provide the compliance needed to compensate for the mismatch in coefficient in thermal expansion (CTE) of the package and PCB. However, in area array devices such as ball grid array (BGA) and chip scale packages (CSP), the joint alone must provide CTE mismatch compliance. This paper addresses the influence of PCB parameters on Chip Scale Package assembly and reliability.

For more information, contact a Universal Sales Rep.